LOW SHEET RESISTANCE GaN CHANNEL ON Si SUBSTRATE USING InAlN AND AlGaN BI-LAYER CAPPING STACK

ABSTRACT

Transistors or transistor layers include an InAlN and AlGaN bi-layer capping stack on a 2DEG GaN channel, such as for GaN MOS structures on Si substrates. The GaN channel may be formed in a GaN buffer layer or stack, to compensate for the high crystal structure lattice size and coefficient of thermal expansion mismatch between GaN and Si. The bi-layer capping stack an upper InAlN layer on a lower AlGaN layer to induce charge polarization in the channel, compensate for poor composition uniformity (e.g., of Al), and compensate for rough surface morphology of the bottom surface of the InAlN material. It may lead to a sheet resistance between 250 and 350 ohms/sqr. It may also reduce bowing of the GaN on Si wafers during growth of the layer of InAlN material, and provide a AlGaN setback layer for etching the InAlN layer in the gate region.

This is a Continuation of application Ser. No. 14/141,304 filed Dec. 26,2013 which is hereby incorporated by reference.

An embodiment of the invention is related to Gallium Nitride (GaN)circuit devices and the manufacture and structure of GaN channel basedcircuit devices. Other embodiments are also described.

BACKGROUND

Increased performance in and yield of circuit devices on a substrate(e.g., integrated circuit (IC) transistors, resistors, capacitors, etc.on a semiconductor (e.g., silicon) substrate) is typically a majorfactor considered during design, manufacture, and operation of thosedevices, or a system on a chip including such devices. For instance,Gallium Nitride (GaN) circuit devices having a GaN channel may be partof a voltage regulator, a power management integrated circuit (IC), aradio frequency (RF) power amplifier, for a system on a chip (SoC)architecture. Design and manufacture (e.g., forming) of such devices mayinclude transistors or transistor layers (e.g., layers of material thatare included in or part of a transistor) of a GaN channel metal oxidesemiconductor (MOS) devices. Such devices may be a GaN MOS-high electronmobility transistor (HEMT).

Such GaN channel devices may include a gate, a gate dielectric, a sourceregion (e.g., junction region), and a drain region (e.g., junctionregion). The conductive channel of the device resides beneath the gatedielectric. Specifically, current runs along/within the channel. For a“fin” device or channel, the conductive channel of such configurationsessentially resides along the three different outer, planar regions ofthe fin. There are a number of non-trivial issues associated withfabricating such GaN channel devices or transistors.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments of the invention are illustrated by way of example andnot by way of limitation in the figures of the accompanying drawings inwhich like references indicate similar elements. It should be noted thatreferences to “an” or “one” embodiment of the invention in thisdisclosure are not necessarily to the same embodiment, and they mean atleast one.

FIG. 1 is a schematic cross section view of a portion of a semiconductorsubstrate base after forming Gallium Nitride (GaN) channel basedtransistor layers including an InAlN and AlGaN bi-layer capping stack ona GaN layer.

FIG. 2 shows details of one example of the GaN buffer layer of FIG. 1.

FIG. 3 shows the semiconductor substrate of FIG. 1 after forming a gate,and junction regions on or in the transistor layers.

FIG. 4 shows a plot of mobility versus AlGaN thickness, and chargedensity versus thickness for Gallium Nitride (GaN) channel basedtransistor layers including an InAlN and AlGaN bi-layer capping stack ona GaN layer.

FIG. 5 is an example process for forming GaN channel based transistorlayers including an InAlN and AlGaN bi-layer capping stack on a GaNlayer.

FIG. 6 is a schematic cross section view of a portion of a semiconductorsubstrate base after forming a Gallium Nitride (GaN) channel basedtransistor having a GaN layer grown out of trenches or gaps in theSilicon substrate; and an InAlN and AlGaN bi-layer capping stack on theGaN layer.

FIG. 7 is a schematic cross section view of a portion of a semiconductorsubstrate base after forming a Gallium Nitride (GaN) channel based fintransistor having a GaN fin layer grown on a Silicon fin; and an InAlNand AlGaN bi-Layer fin Capping Stack on a GaN fin layer.

FIG. 8 is a 3-dimensional (3D) cross section along the fin 790 of aportion of a semiconductor substrate base after forming a GalliumNitride (GaN) channel based fin transistor from layer having a GaN finlayer grown on a Silicon fin; and an InAlN and AlGaN bi-Layer finCapping Stack on the GaN fin layer.

FIG. 9 illustrates a computing device, such as a system on a chip (SoC),in accordance with one implementation.

DETAILED DESCRIPTION

Several embodiments of the invention with reference to the appendeddrawings are now explained. Whenever the shapes, relative positions andother aspects of the parts described in the embodiments are not clearlydefined, the scope of the invention is not limited only to the partsshown, which are meant merely for the purpose of illustration. Also,while numerous details are set forth, it is understood that someembodiments of the invention may be practiced without these details. Inother instances, well-known circuits, structures, and techniques havenot been shown in detail so as not to obscure the understanding of thisdescription.

There are a number of non-trivial issues associated with fabricatingGallium Nitride (GaN) channel devices or transistors. For example, forGaN layers grown on blanket Silicon (Si) substrates, two main challengesto be overcome are lattice mismatch and thermal mismatch between the GaNmaterial and the Si material. There is a high crystal structure latticesize mismatch between GaN and Si (17% for GaN on Si (111) and 41% forGaN on Si (100)); and a large mismatch in coefficient of thermalexpansion between GaN and Si (around 115% for GaN and Si). Due to this,very complicated buffer engineering can be used to maintain low enoughdefect density (˜1E9/cm2) and also to prevent surface cracks due to thethermal mismatch. A typical GaN channel stack structure (e.g., GaNbuffer layer) may include a complex layer stack design for obtaining GaNlayers with low enough defect density and zero surface cracks on Si(100) (e.g., See FIG. 2).

According to some embodiments, a 2-dimensional electron gas (2 DEG)channel can be created in GaN layer of GaN transistors by capping theGaN layer with a single capping layer. The difference in spontaneouspolarization and piezoelectric polarization due to strain in the cappinglayer, may result in the formation of a 2 DEG channel in the GaN layerwith high electronic charge and high mobility. However, certain cappinglayer material grown on top of this buffer stack may suffer from poorcomposition uniformity (e.g., of Al and In of an InAN layer) and roughsurface morphology resulting in the low channel mobility due tointerface scattering and alloy scattering. Also, AlInN alloys are grownat relatively low temperatures by MOCVD (metalorganic chemical vapordeposition) at around ˜700-800 Celsius (C) while GaN is grown at ˜1050 Cby chemical vapor deposition (CVD). The temperature drop to grow anAlInN capping layer may—results also in some bowing of the GaN/Si wafersduring growth further degrading the uniformity of the AlInN layer andhence resulting in low mobility.

Some embodiments described herein provide an InAlN and AlGaN bi-layercapping stack on a 2 DEG GaN channel, such as for GaN MOS-high electronmobility transistor (HEMT) structures on Si substrates. The 2 DEG GaNchannel may be formed in a GaN buffer layer or stack, to reduce orcompensate for the high crystal structure lattice size mismatch andlarge mismatch in coefficient of thermal expansion between GaN and Si.The bi-layer capping stack may use two polarization charge inducinglayers (e.g., InAlN and AlGaN) to reduce or compensate for poorcomposition uniformity (e.g., of Al and In) and rough surface morphologyof the bottom surface of the cap layer of InAlN material. Using twolayers in the bi-layer capping stack may also reduce or compensate forbowing of the GaN/Si wafers during growth of the cap the cap layer ofInAlN material.

In addition, two key requirements may be identified to obtain highperformance GaN transistors which can be used as “power devices” such asa voltage regulator (VR), a power management (PM) integrated circuit(IC), a radio frequency (RF) power amplifier for a system on a chip(SoC). First, it may be desired to have low sheet resistance (Rsh) inthe GaN channel (typically less than or equal to 250 ohms/sqr, a veryaggressive number). Second, it may be desired to have a controlled wayto create E-mode operation for the GaN transistors.

According to some embodiments, a transistor or transistor layers havingthe InAlN and AlGaN bi-layer capping stack on a GaN channel provide lowsheet resistance (Rsh) in the GaN channel and an E-mode operation forGaN transistors (e.g., see the structure or transistor layers of FIG.1). Such transistor layers may be layers of material that are includedin or part of a transistor. Such a transistor may be a GaN MOS-highelectron mobility transistor (HEMT). The transistor may be a flat, thin,or tri-gate transistor; and top surface of the substrate may be singlecrystal silicon having a (100), (111), or (110) Miller Index withsubstrate miscuts ranging from 2-10° along certain preferred directions.The transistor may be part of a voltage regulator, a power managementintegrated circuit (IC), a radio frequency (RF) power amplifier, or asystem on a chip (SoC). Some embodiments include, the GaN channel grownout of trenches in the Silicon substrate. Some embodiments include, aGaN channel based fin transistor having a GaN fin channel grown on aSilicon fin and an InAlN and AlGaN bi-layer capping stack on the GaN finchannel.

Using the bi-layer capping stack may provide a higher channel mobility,higher charge density and lower sheet resistance for a GaN channelhaving a 2 DEG channel or channel portions. For example, a bi-layercapping stack for such transistors may include two 2 DEG channelportions adjacent a gate channel portion (that is not 2 DEG) to providevery low resistance between outer junction regions so that power is notlost or required for such transistors to deliver power from a battery toother circuitry. The lower the sheet resistance in this region, thehigher is the efficiency of the transistor used for power delivery etc.Also, for PMIC and voltage regulator design for SoC using GaNtransistors, a channel with sheet resistance (Rsh) of 250 ohms/sqr andlower can be a beneficial requirement. Also for SoC the GaN layers canbe beneficially co-integrated with Si CMOS on the same wafer, hence adevice or process of creating the GaN channel with the requiredresistance is unique.

For example, two main components that may lead to the low Rsh values forthe 2 DEG channel are: (1) High Electron density which for thiscombination >2.5E13/cm2; and (2) high channel mobility ˜900-1400cm2/V-s. According to some embodiments, an upper AlInN layer in thebi-layer stack may generate the high electron density whereas a lowerAlGaN layer may help in keeping the channel mobility high. Embodimentshaving just an AlGaN cap alone, may not lead to high electron densitylike density >2.5E13/cm2. Also, embodiments having only a InAlN cap onGaN layers grown on Si substrates may result in low channel mobility.However, a bi-layer stack of an upper AlInN layer (specificallyAl_(0.83)I_(0.17)N) and a lower AlGaN layer (where Al<0.4) may providethe low Rsh required for VR and PMIC GaN transistors, such as for SoC.

In some cases, the bi-layer capping stack is formed on or over a topsurface of the GaN layer having the 2 DEG channel, wherein the bi-layercapping stack induces or causes low a sheet resistance in the GaNchannel (e.g., in the 2 DEG channel), such as sheet resistance of <250ohms/sqr; or between 200 and 350 ohms/sqr. In some cases, the AlGaNlayer of the bi-layer capping stack causes electrons in a channel of theGaN material to be subject to less interface roughness scattering andless alloy scattering, and thus provide a higher mobility than withoutthe AlGaN layer.

FIG. 1 is a schematic cross section view of a portion of a semiconductorsubstrate base 101 after forming Gallium Nitride (GaN) channel basedtransistor layers including an InAlN and AlGaN bi-layer capping stack150 on a GaN layer 110. FIG. 1 shows transistor layers 100 includingsubstrate 101 of material 102 having top surface 103. GaN buffer layer110 is formed on top surface 103. GaN layer 110 has 2-dimensionalelectron gas (2 DEG) electron channel 114. Layer 110 has top surface113. AlN layer 120 has top surface 123. Lower layer 130 is formed onsurface 123. Lower layer 130 has top surface 133. Upper layer 140 isformed on surface 133. Upper layer 140 has top surface 143. Substrate101 has thickness TH1; layer 110 has thickness TH2; layer 120 hasthickness TH3; layer 130 has thickness TH4; and layer 140 has thicknessTH5. Channel 114 has a thickness of TH31.

Transistor layers 100 may represent or be layers that are included in afunctional or functioning transistor. In some cases, transistor layers100 may represent or be layers that are included in a structure thatwill be further processed to form a functional or functioning transistor(e.g., see FIGS. 3 and 6-8). In some cases, layers 100 may be part of orused to form a flat, thin, tri-gate, or a GaN MOS-high electron mobilitytransistor (HEMT). The transistor may be part of a voltage regulator, apower management integrated circuit (IC), a radio frequency (RF) poweramplifier, or a system on a chip (SoC).

Substrate 101 may be single crystal silicon substrate having a (100),(111), or (110) Miller Index. In some cases, material 102 is a siliconmaterial having a crystalline structure of (100), (111), or (110) alongsurface 103. In some cases, TH1 may be in a range of between 500 to 1200microns. The Silicon substrate (e.g., Si (100)) may also have a miscutranging from 2-10° along certain preferred directions (e.g., (110)).

Buffer or layer 110 may be a GaN buffer layer or a GaN stack (e.g.,having a 2 DEG channel formed in the GaN buffer layer or stack), toreduce or compensate for the high crystal structure lattice sizemismatch and large mismatch in coefficient of thermal expansion betweenGaN and Si (e.g., see FIG. 2). In some cases, TH2 may be in a range of 1micron and aboves.

Bi-layer capping stack (e.g., structure) 150 may be formed on (e.g.,over or touching) top surface 113 of GaN layer 110. Stack 150 mayinclude, be formed by, or be formed by a process including forming lower(e.g., first or bottom) capping layer 130, which comprises or is anAlGaN material on (e.g., over) top surface 113 of GaN layer 110. In somecases, layer 130 is formed on (e.g., over or touching) top surface 123of GaN layer 120. In some cases, capping layer 130 comprises or is anAlGaN material formed on (e.g., over or touching) top surface 123 of AlNlayer 120 formed on surface 113.

Stack 150 may also include, be formed by, or be formed by a processincluding forming upper (e.g., second or top) capping layer 140, whichcomprises or is an AlInN material on (e.g., over or touching) topsurface 133 of lower layer 130 (e.g., of the AlGaN material). Stack 150has width W1, height H1 and length L1 (not shown but going into thepage).

In some cases, W1 is in a range of between 50 nm and 10 um. In somecases, W1 is in a range of between 50 nm and 500 nm. In some cases, W1is in a range of between 50 nm and 100 nm. In some cases, L1 is in arange that depends on the transistor width, on applications and oncircuit layout. In some cases, L1 is in a range from 5 microns to 20 mm.

According to embodiments, stack 150 is layers 130 and 140. According toother embodiments, stack 150 is layers 120, 130 and 140. According toembodiments, stack 150 includes or consists essentially of is layers 130and 140. According to embodiments, stack 150 includes or consistsessentially of is layers 120, 130 and 140.

In some cases, layer 130 layer is Al_(X)Ga_((1-X))N, where X is lessthan 0.4. In some cases X is equal to 0.3. In some cases X is between0.05 and 0.4. In some cases, TH4 (the AlGaN layer thickness) is ofbetween 2 and 10 nm. In some cases it is between 2-10 nm. In some casesit is between 8-10 nm. In some cases it is 2 nm. In some cases it is 5nm. In some cases, surface 133 (e.g., a top surface of the AlGaNmaterial) forms a uniform and high crystal quality AlGaN materialsurface upon which the AlInN material is formed (e.g., epitaxially grownfrom). The thickness of the AlGaN layer may depend on the composition ofthe AlGaN layer being grown. For higher Al containing AlGaN compoundsthe thickness that can be grown pseudomorphically on the GaN bufferstack is reduced as compared to lower Al containing AlGaN compounds. Insome cases, it is important that the AlGaN layer thickness is kept belowthis “critical thickness” (e.g., 10 nm) as generation of misfitdislocations due to lattice mismatch between 130 and GaN buffer stackwill reduce the channel mobility.

In some cases, layer 140 layer is Al_(Y)In_((1-Y))N, where Y is greaterthan 0.8. In some cases Y is equal to 0.83. In some cases, TH5 (theAlInN layer thickness) is of between 5 and 35 nm. In some cases, TH5 isof between 5 and 30 nm. In some cases, layer 140 induces a channel inGaN with electron mobility between 900 and 1400 cm²/V-s. In some cases,the mobility is 960 cm2/V-s. In some embodiments, X is less than 0.4 andY is greater than 0.2.

According to embodiments, a large band gap between material 140 andmaterial 110 causes a layer of electrons to exist below surface 113 ofmaterial 110. In some cases, layer 130 should also consist of a materialwith band gap greater than that of material 110. This layer of electronsmay cause or be described as 2 DEG electron channel 114. In some cases,channel 114 forms at an interface below layer surface 113, such as byincluding electrons that reside in thickness TH31 below surface 113, andform a channel there that requires no biasing for conduction. The amountof charge carriers and conduction may depend on or be proportional tothe thickness of material 140 and concentration of aluminum in material140. In some cases, TH31 may be in a range of between 1 and 3 nm.

Channel 114 may include an electron channel in the which is confined inone dimension due to a quantum well formation, such as a two-dimensionalsheet of electron charge that has higher mobility and requires less orzero gate voltage for conduction than a MOS channel. In some caseschannel 114 does not require doping due to the crystal structure oflayer 140 providing an electron density within channel 114 due topolarization effects. Thus it may not be necessary to form a gate ormetal layer over layer 130 or 140 to create carrier conduction withinchannel 114, which means that the transistor would be “on” without anygate voltage. However, it may be necessary to apply a bias voltage ongate to induce charge if layer 140 is removed from stack 150.

According to some embodiments, the InAlN and AlGaN bi-layer cappingstack on a GaN channel provides low sheet resistance (Rsh) in the GaNchannel. In some cases, layer 120 is a thin layer of AlN that helpscause electrons in a channel of the GaN material to be subject to lessinterface roughness scattering and less alloy scattering, and thusprovide a higher mobility than without the AlN layer. In some cases,layer 120 may be thickness TH3 in a range of between 0.6 and 1.5nanometers. In some cases, layer 120 has a thickness TH3 of 1 nm. Insome cases, TH3 is 1.2 nanometers or less than 1.2 nanometers.

In some cases, layer 130 (or layer 130 and layer 120) causes electronsin channel 114 (e.g., 2 DEG of the GaN material) to be subject to lessinterface roughness scattering and less alloy scattering, and thusprovide a higher mobility in channel 114 than without the AlGaN layer(e.g., than with only layer 140, without layer 130). Layer 130 may havethickness TH4 that is thin enough so that there are not many carriers ormuch general conduction in layer 130 and also does not create misfitdislocations due to the lattice mismatch between 130 and 110.

In some cases, the non-uniformity of aluminum and indium in layer 140would lead to more scattering of electrons and less mobility without theuse of layer 130 which has a more uniform distribution of aluminum alongthe length and width of layer 130 (e.g. perpendicular to thickness TH4).In some cases, since layer 140 may be non-uniform or rough with respectto concentrations of aluminum and indium within layer 140, layer 130 mayprovide a smoother and higher quality material that provides increasedmobility in channel 114 since the uniformity of aluminum in layer 130may be more homogenous and continuous (e.g. smooth). The more homogenousor smooth consistency of reduces the alloy scattering and interfaceroughness scattering of electrons in channel 114. Layer 120 may reducealloyed scattering in channel 114, as compared to having layer 130touching or on surface 113 or channel 114.

In some cases, bi-layer capping stack 150 causes or induces a sheetresistance of less than or equal to 250 ohms per SQR in channel 114(e.g., across W1, between left and right ends of that channel). In somecases, bi-layer capping stack 150 causes or induces a sheet resistanceof between 200 and 300 ohms per SQR in channel 114. In some cases, thissheet resistance of R ohms per SQR is defined for or across the width W1of stack 150 and L1

Sheet resistance may be the resistance is given by: R=Rho*W1/A where Rhois the resistivity of a sample of material (e.g., layers 130 and 140),and W1 and A are its width and cross-sectional area (e.g., H1×L1),respectively. If L1 is the length of the sample and H1 is its thicknessor height (i.e., A=L1×H1), then the resistance can be written:R=(Rho/H1) (W1/L1)=Rs(W1/L1) where Rs=Rho/H1 is the sheet resistance ofa layer of this material. Strictly speaking, the unit for sheetresistance may be the ohm (since W1/L1 is unitless). To avoid confusionbetween R and Rs, however, sheet resistance may be specified in unit of“ohms per square.” The W1/L1 ratio can be thought of as the number ofunit squares (of any size) of material in the resistor (e.g., layers 130and 140).

According to some embodiments, the InAlN and AlGaN bi-layer cappingstack on a GaN channel reduces or compensates for bowing of the GaN/Siwafers during growth of the cap material. It is noted that AlInN alloysare typically grown at relatively low temperatures by MOCVD(metalorganic chemical vapor deposition) at around ˜700-800 C while GaNis grown at ˜1050 C by CVD. Without layer 130, the temperature drop togrow the AlInN layer 140 may result in some bowing of the GaN/Si wafersduring growth further degrading the composition uniformity of the AlInNlayers and hence resulting in low mobility.

According to some embodiments, the InAlN and AlGaN bi-layer cappingstack on a GaN channel provides a “setback” material surface for etchingan opening for the gate. For example, in some cases, layer 130 (e.g.,surface 133; a top surface of the AlGaN material) forms a “setback”material surface. As a “setback” layer, layer 130 (e.g., surface 133)may be a layer that can be used as an etch stop, so that other layers(e.g., material of layer 140) may be selectively etched with respect tomaterial of layer 130. For example, in some cases, stack 150 includeslayers 130 and 140 (and optionally layer 120) at or under the junctionregions and in portions 340 and 342; while only layer 130 (andoptionally layer 120) of stack 150 (e.g. not layer 140) exists under thegate (e.g., see FIGS. 3 and 6-8). In these cases, layer 140 may beselectively etched to form a trench for a gate.

Thus, including the AlGaN layer 130 (which is grown at 1000-1050 C) actsas a nice setback layer, which is both uniform and of high crystalquality and thus preserves the high mobility of the electron channel inthe GaN layer. These are some ways the layers of the bi-layer stack mayact in unison to result in high charge density and high mobilitysimultaneously for GaN channels grown on Si substrates.

According to some embodiments, the InAlN and AlGaN bi-layer cappingstack on a GaN channel also provides an E-mode operation for GaNtransistors. For example, for a transistor to be used as part of avoltage regulator, power management IC or RF power amplifier, onedesired mode of operation is as an E-mode transistor which means atransistor with Vt>0 V. To make an E-mode transistor in GaN, typicallythe capping layer is etched off under the gate (e.g., forming trench305). For single capping structures (e.g., without both layer 130 and140 prior to etching to form trench 305), the etch is typically done bya dry etch and is timed, there are no etch-stops. This of course leadsto yield issues and can result in low channel mobility due to over etchor etch damages. The bi-layer stack has a great advantage in that aspecttoo, AlInN can be selectively wet etched under hot KOH or NH40Hsolutions, while the AlGaN layer is not. Since all or at least 90percent of the electronic charge is due to the AlInN layer, completeremoval of it results in obtaining E-mode operation. Thus the processcan be very well controlled and also the channel mobility is notcompromised due to over etch or dry etch damages.

Using a GaN buffer or stack may reduce or compensate for the highcrystal structure lattice size mismatch and large mismatch incoefficient of thermal expansion between GaN and Si. In some cases,layer 110 has or is a GaN stack of multiple GaN layers separated by AlNlayers. Each adjacent pair of adjacent (e.g., vertically adjacent orstacked) GaN layers may be separated by a thinner AlN layer. There mayalso be an AlN layer between the bottom GaN layer and the substrate. Insome cases, layer 110, or the GaN buffer layer or stack (e.g., see FIG.2) has a defect density less than or equal to 1 E9/cm2 (e.g., withinTH31 or channel 114).

FIG. 2 shows details of an example of the GaN buffer layer 110 ofFIG. 1. FIG. 2 shows layer 110 having AlN layers 230, 250 and 270 formedbetween GaN layers 220, 240, 260 and 280. AlN layer 210 is formedbetween top surface 103 and a bottom surface of layer 220 (e.g., thebottom GaN layer).

Layer 110 may include layer 210 (and other AlN layers) due to the largelattice mismatch between silicon material 102 and GaN material withinlayer 110. For example, layer 210 may reduce, prevent, or provide abuffer between surface 103 and material 102 and layer 220. Layer 210 mayalso trap silicon defects and reduce lattice mismatch defects fromreaching layer 220. Layer 210 may also reduce chemical reaction betweenmaterial 102 and the GaN material of layer 220.

In some cases, layer 210 may be a nucleation layer grown on substrate100, for example, to help begin growth on layer 101 of one or morelayers of semiconductor material (e.g., one or more III-N semiconductormaterials such as GaN, AlN, AlGaN, AlInN, etc., which may form layer101). In some cases in which substrate 101 comprises Si(100), forexample, nucleation layer 210 may comprise a semiconductor material suchas, but not limited to, aluminum nitride (AlN), AlGaN, an alloy of anyof the aforementioned, and/or a combination of any of theaforementioned. In some embodiments, nucleation layer 210 may have athickness in the range of about a monolayer to about 300 nm or greater(e.g., about 100-200 nm or greater, or any other sub-range within therange of about 1-300 nm or greater).

In some cases, layer 220 includes a lower 3 dimensional crystalstructure that is grown as islands on surface 213 of layer 210; andupper 2 dimensional crystal structure. Such islands may be between 50and 250 nm wide or in diameter. Such islands may be approximately 100nanometers in diameter. Such islands may be approximately 100-250nanometers in height or thickness. For instance, in some exampleembodiments, three-dimensional islands may have a thickness in the rangeof about 1-250 nm or greater (e.g., about 50-100 nm or greater; about100-150 nm or greater; about 150-200 nm or greater; about 200-250 nm orgreater; or any other sub-range within the range of about 1-250 nm orgreater).

In some cases, such islands may be grown or located sufficientlyproximate one another on surface 213 so as to generally overlap orotherwise merge with another while remaining substantially discrete.This may avoid forming a continuous layer across the underlying topologyof nucleation layer 210.

In some embodiments, such islands can be formed by growing the islandsin trenches (e.g., represented by features 614, 616 and 618 FIG. 6)between insulator patches (e.g., represented by features 612, 615, 617and 619 FIG. 6) formed on surface 213 of layer 210 (e.g., see FIG. 6).In some embodiments, such islands can be formed by being forced to growin a three-dimensional mode by in-situ patterning. Such islands may begrown on or from surface 213 between a plurality of small features(e.g., in-situ islands, patches, etc.) of insulator which may help toensure that subsequent formation of the islands of are three-dimensional(e.g., consists of a plurality of island-like semiconductor structures).In some example instances, these small, patchy features of insulatorlayer (e.g., represented by features 612, 615, 617 and 619 FIG. 6) mayhave a thickness (e.g., a height/depth) in the range of about 10 nm orless (e.g., about 5-10 nm or less; about 1-5 nm or less; a monolayer;etc.). By virtue of providing such an optional insulator features, theisland-like structures may be caused to grow or otherwise form betweenthe features thereof.

In some embodiments, such islands can be formed by growing the islandsas nanowires in gaps (e.g., represented by features 614, 616 and 618FIG. 6) between insulator (e.g., represented by features 612, 615, 617and 619 FIG. 6) formed on surface 213 of layer 210. In some embodiments,such islands can be formed by being forced to grow in athree-dimensional mode by ex-situ patterning. In some cases, aninsulator layer formed on surface 213 may be patterned with one or moregap features which may help to ensure that subsequent formation ofsemiconductor layer is three-dimensional (e.g., consists of a pluralityof nanowires). In accordance with embodiments, the dimensions of a givengap feature (e.g., represented by features 614, 616 and 618 FIG. 6) maybe customized as desired, and in some example instances may have a widthin the range of about 1-250 nm or greater. In some instances, a givengap feature may have a height/depth in the range of about 1-250 nm orgreater. By virtue of providing such an optional insulator layer, thenanowires may be caused to grow or otherwise form within gap featuresand to broaden/expand therefrom. In some cases, a given nanowire mayhave a width in the range of about 1-250 nm or greater. Also, in someembodiments, a given nanowire may have a height/depth in the range ofabout 1-250 nm or greater.

Such 3 dimensional crystal structure islands may reduce defects in theupper 2 dimensional crystal structure (e.g., layer 220). After formingsuch islands, an upper 2 dimensional crystal structure may be grown onthe islands. The upper 2 dimensional crystal structure may be grown asblanket layer. The upper 2 dimensional crystal structure may have athickness of between 50 nm and 5 micro meters. The upper 2 dimensionalcrystal structure may have a thickness of between 1.2 and 1.5 micrometers. The upper 2 dimensional crystal structure may have a thicknessof 900 nm. One example of the upper 2 dimensional crystal structure mayinclude or be layers 220-280 (e.g., excluding the islands).

Next, FIG. 2 shows an example layer 110 having AlN layers 230, 250 and270; and GaN layers 240, 260 and 280 formed on layer 220 (e.g., formedon the upper 2 dimensional crystal structure). Layers 230, 250 and 270may buffer or compensate for the large thermal mismatch between the GaNmaterial of layer 110 and that of Si substrate 101. In some cases,during forming of layer 110, layer 110 is formed in a convex, crosssectional shape, so that when layer 110 reaches operating temperature,layer 110 forms a flat layer with reduced cracking due to the thermalmismatch between the GaN material of layer 110 and that of substrate101. In some embodiments, substrate 103 has Miller Index (100).

In some embodiments, layer 210 has a thickness of between 50 and 350 nm;layer 220 has a thickness of between 90 and 1500 nm; layer 230 has athickness of between 5-25 nm16 and 18 nm; layer 240 has a thickness ofbetween 100-400 nm 218 and 268 nm; layer 250 has a thickness of between5-25 nm, layer 260 has a thickness of between 100-450 nm, layer 270 hasa thickness of between 5-25 nm; and layer 280 has a thickness of between400 and 900 nm thick. In some embodiments, layer 210 has a thickness of247 nm; layer 220 has 3D GaN of approximately 100 nm and GaN of 900 nm.In this embodiment, layer 230 is approximately 16 nm; layer 240 is 243nm; layer 250 is 9.4 nm; layer 260 is 383 nm; layer 270 is 5.6 nm; andlayer 280 is 570 nm thick.

In some cases, layer 110 has or is a stack of multiple layers of one ormore III-N semiconductor materials such as GaN, AlN, AlGaN, AlInN, etc.For instance the GaN layers of layer 110 described above may representlayers of AlGaN having a low concentration of Al, such as below 10percent Al (e.g., sometimes below 5 percent); and the AlN layers oflayer 110 described above may represent layers of AlGaN or AlInN havinga low concentration of Ga or In, such as below 10 percent Ga or In(e.g., sometimes below 5 percent).

In some embodiments, a given semiconductor layer of layer 110 may have athickness, for example, in the range of about 1-100 nm or greater (e.g.,about 20 nm or less; about 50 nm or less; about 80 nm or less; or anyother sub-range within the range of about 1-100 nm or greater). In someexample cases in which a given semiconductor of layer 110 comprisesAlGaN having a high concentration of Al (e.g., greater than about 95%),for instance, such semiconductor layer may have a thickness in the rangeof about 1-20 nm. In some example cases in which a given semiconductorof layer 110 comprises AlGaN having a low concentration of Al (e.g.,less than or equal to about 5%), for instance, such semiconductor layermay have a thickness in the range of about 10-1000 nm.

FIG. 3 shows the semiconductor substrate of FIG. 1 (e.g., layers 100)after forming transistor 300 including gate 380, junction region (e.g.,source) 360 and junction region (e.g., drain) 370 on or in thetransistor layers. FIG. 3 shows a portion of a semiconductor substratebase 101 after forming a Gallium Nitride (GaN) channel based transistor300 having a GaN layer 310 formed from layer 110; and an InAlN and AlGaNbi-layer capping stack (e.g., stack 351 with trench 305) on the GaNlayer. For transistor 300, stack 351 may be equal to stack 150 includingtrench 305 etched or disposed through layer 140 and to layer 130.Consequently, transistor 300 includes layer 310 having 2 DEG channels314 and 315 adjacent to channel 316 below gate 380. Channel 316 excludesa 2 DEG channel because layer 140 does not exist above channel 316.

FIG. 3 shows trench 305 etched in layer 140 to form separate portions340 and 342 of layer 140. Trench 305 is etched to expose top surface 333of layer 130 having width W2 (and length L2 going into the page but notshown) of surface 133 of layer 130. High-K dielectric layer 350 isformed, conformally, (1) over top surface 143 of portions 340 and 342;(2) on sidewalls 313 and 315 of portions 140 and 142 in trench 305; and(3) on exposed surface 333. Layer 350 has thickness TH6, which may beequal to between 1 and 15 nm.

FIG. 3 shows channel 314 and 315, such as channel 114, under portion 340and 342, respectively, of stack 351. Layer 310 may be similar to layer110 except that channel 114 does not exist at channel 316 due to theremoval of layer 140 in trench 305; and channel 114 does exist aschannels 314 and 315 respectively where layer 140 does exist adjacent totrench 305. Channel 316 is shown without or not including channel 114(e.g. channel 314 or channel 315). Channel 316 may exclude a 2 DEGelectron channel due to not having layer 140 above channel 316. Thus, itis necessary to bias channel 316 to create conduction or carriermovement between a portion 340 and portion 342. This may be described asrequiring a threshold voltage greater than zero volts (e.g. operation isa E-mode transistor operation). In some cases, such E-mode is as knownin the art. In some cases, layer 140 is selectively etched away withintrench 305 to remove the 2 DEG channel from channel 316 so that thethreshold voltage is required to activate the channel or activate thetransistor. In some cases, selectively etching layer 140 (e.g., theAlInN material) includes selectively etching the AlInN material using awet etch including a KOH or a NH4OH solution to selectively etch theAlInN material but not etch (e.g., with the exception of etching) theAlGaN material. Layer 130 may be used as a setback layer for this etch.

In some cases, bi-layer capping stack 351 causes or induces a sheetresistance of less than or equal to 250 ohms per SQR in the combinationof the 2 DEG channels 314 and 315 (e.g., excluding channel 316). In somecases this resistance may be across W1, between left and right ends ofthe channel of the combination of channels 314 and 315 (excludingchannel 316). In some cases, bi-layer capping stack 351 causes orinduces a sheet resistance of between 200 and 300 ohms per SQR in thecombination channel.

Dielectric 350 may be or include a High-K material. Dielectric 315 maybe formed of aluminum oxide, hafnium oxide, tantalum silicon oxide,zirconium oxide, etc. In some cases, layer 350 is or includes Al₂O₃,HfO₂, TaSiOx, ZrO₂, or a combination of these. Dielectric 350 may have athickness of between 1 and 15 nanometers.

Gate structure 380 is shown formed on layer 350 in trench 305 overexposed surface 333. Structure 380 may include a metal gate. Gatestructure 380 may be formed on a top surface of the AlGaN layer 350 byselectively etching the AlInN material to expose a top surface of theAlGaN material (e.g., surface 113 or 133, which may be below 113); andforming a gate dielectric 350 over the exposed surface of the AlGaNmaterial (and sidewalls 313 and 315 and surface 143). Structure 380 maybe formed over dielectric 350 in the trench and over the dielectric onportions 340 and 342 (e.g., in trench 305 and on portions of portions340 and 342). Gate metals that might be used are Ti, Ni, Pt, TiN, W, Au,or combinations of these.

Junction 360 and 370 may extend through channel 314 and 315respectively. Thus the junction regions may be in direct contact withchannel 314 and 315 to reduce resistance of the transistor duringoperation. Junction region or source 360 is shown formed on surface 303of layer 310 adjacent to portion 340, opposite (e.g., to the left ofchannel 314) of trench 305 (e.g., gate 380). Junction region or drain370 is shown formed on surface 303 of layer 310 adjacent to portion 342,opposite (e.g., to the right of channel 315) of trench 305 (e.g., gate380). Surface 303 may formed by thickness 31 of surface 113; and may beat or below channel 114. Region 360 may be an N+ GaN/InGaN sourceregion. Region 370 may be an N+ GaN/InGaN drain region. Region 360 and370 may have a thickness of between 10 and 200 nm.

FIG. 3 shows metal 362 on junction 360, and metal 372 on junction 370.Metal 362 and 372 can be used as a contract to the junction regions, asknown in the art.

FIG. 4 shows a plot 400 of 2 DEG channel carrier mobility 420 versusAlGaN capping layer thickness 430 (e.g., TH4), and 2 DEG channel carriercharge density 410 versus thickness 430 for Gallium Nitride (GaN)channel based transistor layers (e.g., layers 100) including an InAlNand AlGaN bi-layer capping stack (e.g., stack 150) on a GaN layer (e.g.,layer 110). The mobility and density may be for channel 114, but havingstack 150 as noted below.

Plot 400 shows how the mobility and charge density change with insertionof the AlGaN layer 130 (e.g., as opposed to using only layer 140) tomake the bi-layer stack. The mobility points refer to mobility and aremeasured on the right hand axis 420. The charge density points in thegraph refer to the charge density of left hand axis 410. Thus, FIG. 4shows a plot 400 of mobility 420 versus AlGaN thickness 430 on theright-hand axis, and charge density 410 versus thickness 430 on theleft-hand axis.

FIG. 4 shows plotted point 442 as the plot of charge density 410 for anembodiment without layer 130 (e.g., without an AlGaN layer); and plottedpoint 444 as a plot of the mobility for that embodiment. Plot 400 showsplotted point 452 as the plot of charge density 410 for an embodimentwith layer 130 (e.g., with an AlGaN layer) with a 2 nm thickness betweenan AlInN of 7 nm and an AlN layer of 1 nm; and plotted point 454 as aplot of the mobility for that embodiment. Plot 400 shows plotted point462 as the plot of charge density 410 for an embodiment with layer 130(e.g., with an AlGaN layer) with a 5 nm thickness between an AlInN of 7nm and an AlN layer of 1 nm; and plotted point 464 as a plot of themobility for that embodiment.

For the last bi-layer stack combination of 7 nm AlInN (83% AI and 17%In) and 5 nm AlGaN (30% Al) a mobility of 960 cm2/V-s (point 464) andcharge density of 2.5E13 cm-2 (point 462) leads to the desired Rsh of˜250 ohms/sqr. It can be seen that with increasing thickness of theAlGaN layer (e.g., TH4) the mobility steadily improves for the bi-layercapping stack (e.g., stack 150, 351 or 750). For a single cap devicestack of only AlInN, although the charge is very high (point 442) themobility is around 450 cm2/v-s (point 444) resulting in Rsh of >500ohms/sqr, which are not sufficient for SoC transistor targets. An Rsh of˜250 ohms/sqr may be the lowest observed Rsh GaN channel made on Si(100) substrates.

FIG. 5 is an example process for forming GaN channel based transistorlayers including an InAlN and AlGaN bi-layer capping stack on a GaNlayer or channel. FIG. 5 may show process 500 for forming or forming aportion of layers 100, transistor 300, transistor 600 or transistor 700.In some cases process 500 is a process for forming a Low SheetResistance GaN Channel on Si Substrates Using InAlN and AlGaN bi-layercapping stack (e.g., see the “structure” of FIGS. 1, 3, 6-8) forinducing low Rsh channel. In some cases process 500 is a process forforming a flat, thin, or tri-gate transistor that is or is part of avoltage regulator, a power management integrated circuit (IC), a radiofrequency (RF) power amplifier), or a system on a chip (SoC).

FIG. 5 shows process 500 beginning with block 510 where, in someoptional cases, a GaN channel layer is formed on a top surface of asubstrate. Block 510 may include forming the GaN layer comprises a GaNstack having a plurality of GaN layers separated by AlN layers, and anAlN layer between the top surface of the substrate and a bottom GaNlayer. Block 510 may include descriptions above with respect to layer110, 310, 610 or 710.

Next, at block 520, a first, lower or bottom capping layer that is orincludes an AlGaN material is formed on or over the top surface of theGaN layer. Block 520 may include forming a layer of AlN material betweena top surface of the GaN layer and a bottom surface of the AlGaN layer.Block 520 may include descriptions above with respect to layer 120, 130or 730. In some cases, the AlGaN layer has a thickness of between 2 and10 nm, and an electron density of greater than 2.5 E13 cm/2. In somecases, the AlGaN layer comprises Al_(X)Ga_((1-X))N, where X is less than0.4 (or X is between 0.35 and 0.4). In some cases, block 520 includedescriptions above with respect to layer 130 or 730.

Next, at block 530, a second, upper or top capping layer (e.g., withrespect to the bottom capping layer) that is or includes an AlInNmaterial is formed on or over the top surface of the AlGaN layer. Insome cases, the AlInN layer has a thickness of between 5 and 15 nm, anda channel mobility of between 900 and 1000 CM2. In some cases, the AlInNlayer is Al_(Y)In_((1-Y))N, where Y is less than 0.2 (or is equal to0.17). In some cases, a top surface of the AlGaN material forms asetback material surface upon which the AlInN material may beselectively etched. Block 520 may include descriptions above withrespect to layer 140 or 740.

In some cases blocks 520 and 530 may describe forming a bi-layer cappingstack on or over a top surface of the GaN layer, wherein the bi-layercapping stack, has a sheet resistance of less than or equal to 250 ohmsper SQR; or between 250 and 350 ohms per SQR across the width of the 2DEG channel. In some cases, the AlGaN layer causes electrons in achannel of the GaN material to be subject to less interface roughnessscattering and less alloy scattering, and thus provide a higher mobilitythan without the AlGaN layer.

In some cases, block 510 includes forming the GaN layer in a chamber ata temperature of approximately 1050 degrees Celsius (C); block 520includes forming the AlGaN layer a chamber at a temperature of between1000 and 1050 degrees C.; and block 530 includes forming the AlInN layerin a chamber at a temperature between 700 and 750 degrees C. In somecases, a top and bottom surface of the GaN, AlGaN, and AlInN layersinclude smooth surfaces. In some cases, blocks 510, 520 and 530 describeforming transistor layers for a GaN channel transistor.

Next, at block 540, in some optional cases, a transistor is formed fromthe transistor layers. Block 540 may include forming a gate on or over(e.g., on a dielectric layer formed on a top surface of the AlGaN layer.In some cases, forming the gate includes selectively etching the AlInNmaterial to expose a top surface of the AlGaN material; and forming agate dielectric over the exposed surface of the AlGaN material.Selectively etching the AlInN material may be by using a wet etchincluding a KOH or a NH4OH solution to selectively etch the AlInNmaterial with the exception of (e.g., but not etch) the AlGaN material.Block 540 may include descriptions above with respect to trench 305,layer 350, gate 380 or region 780.

Block 540 may optionally include forming junction regions (e.g., sourceand drain) on or over the AlInN layer. In some cases, the thresholdvoltage for activating or turning on the transistor (Vt) is greater than0 volts.

According to embodiments, process 500 only includes blocks 520 and 530.According to embodiments, process 500 only includes blocks 510, 520 and530. According to embodiments, process 500 only includes blocks 520, 530and 540.

According to embodiments, the descriptions above for FIG. 1-5 can beapplied to other types of transistors such as a tri-gate transistor, ortransistors having a GaN channel formed by other processes.

According to some embodiments, the bi-layer capping stack 150 is usedinstead of growing AlInN 140 directly on the GaN buffer 110 on Si (100)substrate 101. This avoids the non-uniformity of the AlInN layer(especially close to the GaN channel) which could be responsible for lowmobility observed in the GaN channel, without layer 130. By inserting auniform AlGaN layer 130 (and optionally, layer 120) before the AlInNlayer 140, the electrons in the channel 114 are subject to lessinterface roughness scattering and alloy scattering, and a high mobilityis obtained.

In some cases, the AlGaN layer 130 is kept thin, as high Al compositionAlGaN (e.g., 35-40% Al) has a critical layer thickness of ˜8-10 nm onGaN before it starts to create dislocations and defects in the GaN. Alsothe AlGaN layer has to be uniform and high quality so as to maintain thehigh channel mobility. Some embodiments also include layer 120 tofurther smoothen or homogenize the percentage of Al at surface 113, thusreducing alloy scattering. In some cases, the AlInNI AlGaN bi-layerstack includes very smooth surface morphology of the bi-layer stack,again highlighting the benefit of the AlGaN layer in obtaining a smoothfinal epi-surface. In some cases, the embodiments herein are related tofabrication of type III-V and Si substrate or channel devices that areproduced for use in personal computers, tablet computers, smartphone,power management and communication devices.

FIG. 6 is a schematic cross section view of a portion of a semiconductorsubstrate base 101 after forming a Gallium Nitride (GaN) channel basedtransistor 600 having a GaN layer 610 grown out of trenches or gaps inthe Silicon substrate (e.g., see portions 614, 616 and 618 of GaN); andan InAlN and AlGaN bi-layer capping stack (e.g., stack 351 with trench305) on the GaN layer. For transistor 600, stack 351 includes trench 305etched or disposed through layer 140 and to layer 130. Consequently,transistor 600 includes layer 610 having 2 DEG channels 314 and 315adjacent to channel 316 below gate 380.

Layer 610 is shown having thickness TH2 and thickness TH21 of oxideregions 612, 615, 617 and 619 on surface 103. Between the oxide regionsmaterial 610 has GaN regions 614, 616, and 618. The oxide regions havewidth W4, such as a width between 50 and 1000 nanometers. Regions 614,616 and 618 have width W3, such as a width between 20 and 1000nanometers. Thickness TH21 may be between 20 and 200 nanometers. In somecases, the thickness, spacing and width of the oxide (e.g., regions 612,615, 617 and 619) will be determined by the dimensions of the GaNTransistor 600. Layer 610 may represent a trench growth of GaN materialbetween the oxide regions, such as where region 614, 616, and 618 aregrown from surface 103 between the oxide regions (e.g., see descriptionsof FIG. 2 for the 3D islands or nanowires and 2D layer of layer 220).Such growth may extend above surface 113 and then be plainarized (e.g.,the 2D layer) to form surface 113. Transistor 600 may have a GaN channelgrown out of Trenches to form a planar GaN transistor using Bi-layercomposite stack 150.

FIG. 7 is a schematic cross section view of a portion of a semiconductorsubstrate base 101 after forming Gallium Nitride (GaN) channel based fintransistor layers 702 having a GaN fin layer 710 grown on a Silicon fin701; and an InAlN and AlGaN bi-Layer fin Capping Stack (e.g., fin stack750 with recessed gate region 780) on the GaN fin layer. FIG. 8 is a 3Dcross section along the fin 790 of a portion of a semiconductorsubstrate base 101 after forming a Gallium Nitride (GaN) channel basedfin transistor 700 from fin transistor layers 702 having a GaN fin layer710 grown on a Silicon fin 701, and an InAlN and AlGaN bi-Layer finCapping Stack (e.g., fin stack 750 with recessed gate region 780) on theGaN fin layer. FIG. 8 may show a perspective cross-section view alongthe fin of the GaN channel based fin transistor of FIG. 7. Transistor700 may be a Trigate version of transistor 300, using the Bi-layerComposite Stack 750.

FIG. 7 shows fins 790 including fin transistor layers 702 having InAlNand AlGaN bi-layer capping stacks 750, formed on fins 701. In somecases, transistor layers 702 may be for function similar to layer 100,but be formed in a “fin” shape such as for a fin transistor. Stack 750may be similar to stack 351, but be formed in a “fin” shape such as fora fin transistor. For fin transistor layers 702, stack 750 includesrecessed gate region 780 having width W5 etched or disposed throughlayer 140 and to layer 130 around 3 sides of fin 790. Consequently, fintransistor layers 702 include layer 710 having 2 DEG channels 714 and715 (e.g., similar to channels 314 and 315 but around 3 sides of fin790); and adjacent to channel 716 (e.g., similar to channel 316 butaround 3 sides of fin 790) below recessed gate region 780. Channel 716may exclude a 2 DEG channel because layer 740 does not exist abovechannel 716.

Fins 790 (or fin transistor layers 702) may include fins 701, layers710, layer 730, and layer 740 formed around 3 sides of fin 790. Fins 701may be formed on surface 703 of substrates 101. In some cases, fins 701are formed by etching surface 103 of substrate 101. Fins 701 may besilicon fins, having a thickness of between 10 and 20 nanometers. Layer710 may be grown on (e.g., epitaxially) or deposited on surfaces of fin701. Fin 701 may include material 102 and may have surfaces similar tosurfaces 103. Material 710 may be formed of material described for layer110. In some case, material 710 includes 1 or more layers described forlayer 110 (e.g., see FIG. 2). Layer 730 is formed on or over layer 710.In some cases, an AlN fin layer such a layer similar to layer 120 formedaround 3 sides of fin 790, is formed between layer 730 and layer 710.This AlN layer may have a thickness similar to that of layer 120.

FIGS. 7 and 8 show shallow trench isolation (STI) oxide 760 formed onsurface 703 of substrate 101. Layer 760 may have top surface 763 uponwhich layer 710, 730 and 740 touch or are disposed above.

Layer 730 may be of similar material, formed by a similar process andhave a similar function as that of layer 130. Layer 740 is shown formedon layer 730. Layer 740 may be of similar material, formed by a similarprocess and have a similar function as that of layer 140.

Layer 710 may be a layer of GaN having a thickness of between 10 and 100nanometers. Layer 730 may be a layer of AlGaN material having athickness of between 2 and 10 nanometers. Layer 740 may be a layer ofAlInN having a thickness of between 5 and 10 nanometers.

FIG. 8 shows transistor 700 including fin transistor layers 702 (e.g.,fin 790) and recessed gate region 780. Recessed gate region 780 may be aregion where layer 740 is etched away to expose surface 733 or layer730. A gate may be formed on region 780, such as to form a thintransistor.

FIG. 8 shows junction region 770, such as a source or drain region. Itcan be appreciated that another junction region may be formed on theother end of transistor 700.

In some cases, bi-layer capping stack 750 causes or induces a sheetresistance of less than or equal to 250 ohms per SQR in the combinationof the 2 DEG channels 714 and 715 (e.g., excluding channel 716). In somecases this resistance may be across W6, between left and right ends ofthe channel of the combination of channels 714 and 715 (excludingchannel 716). In some cases, bi-layer capping stack 751 causes orinduces a sheet resistance of between 200 and 300 ohms per SQR in thecombination channel.

Thus, the devices and processes described herein provide higher channelmobility, charge density and lower sheet resistance for a GaN channeldevice (e.g., having a 2 DEG channel or channel portions). In somecases, layers 100, transistor 300, transistor 600 or transistor 700 maybe or be part of a voltage regulator, a power management integratedcircuit (IC), a radio frequency (RF) power amplifier, or a system on achip (SoC). In some cases, such an SoC may be or include FIG. 9, and mayinclude transistors for power delivery, in contact with a battery,providing power to circuitry of a system on a chip, or of a SoC. A SoCmay have battery power management (e.g. power on, power off, and powervoltage source transistors) on the same chip with logic transistors,memory transistors, communications transistors (e.g. RF amplifiers),and/or other electronics and logic.

It may be desirable for such transistors to have very low resistancebetween junction regions so that power is not lost or required for thetransistors to deliver power to the circuitry, from the battery. In somecases, using transistor layers 100, transistor 300, 600, or 700 havingstack 150, provides low sheet resistance, as noted herein, for suchtransistors.

FIG. 9 illustrates a computing device 900, such as a system on a chip(SoC), in accordance with some implementations. The computing device 900houses board 902. Board 902 may include a number of components,including but not limited to processor 904 and at least onecommunication chip 906. Processor 904 is physically and electricallyconnected to board 902. In some implementations at least onecommunication chip 906 is also physically and electrically connected toboard 902. In further implementations, communication chip 906 is part ofprocessor 904.

In some cases, FIG. 9 illustrates a computing device 900 including asystem on a chip (SoC) 902, in accordance with one implementation. Insome cases, FIG. 9 shows an example of a Systems on a chip (SoC)technology (e.g., motherboard 902). Such a SoC may include amicroprocessor or CPU, as well as various other components, includingelectronics and transistors for power and battery regulation; radiofrequency (RF) processing, receipt and transmission; voltage regulation;power management; and possibly other systems such as those that may befound in a cellular telephone, etc. FIG. 9 may include one or more oftransistor layers 100, transistor 300, 600, or 700 having stack 150,thus providing low sheet resistance, as noted herein.

Depending on its applications, computing device 900 may include othercomponents that may or may not be physically and electrically connectedto board 902. These other components include, but are not limited to,volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flashmemory, a graphics processor, a digital signal processor, a cryptoprocessor, a chipset, an antenna, a display, a touchscreen display, atouchscreen controller, a battery, an audio codec, a video codec, apower amplifier, a global positioning system (GPS) device, a compass, anaccelerometer, a gyroscope, a speaker, a camera, and a mass storagedevice (such as hard disk drive, compact disk (CD), digital versatiledisk (DVD), and so forth).

Communication chip 906 enables wireless communications for the transferof data to and from computing device 900. The term “wireless” and itsderivatives may be used to describe circuits, devices, systems, methods,techniques, communications channels, etc., that may communicate datathrough the use of modulated electromagnetic radiation through anon-solid medium. The term does not imply that the associated devices donot contain any wires, although in some embodiments they might not.Communication chip 906 may implement any of a number of wirelessstandards or protocols, including but not limited to Wi-Fi (IEEE 802.11family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution(LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT,Bluetooth, derivatives thereof, as well as any other wireless protocolsthat are designated as 3G, 4G, 5G, and beyond. Computing device 900 mayinclude a plurality of communication chips 906. For instance, a firstcommunication chip 906 may be dedicated to shorter range wirelesscommunications such as Wi-Fi and Bluetooth and a second communicationchip 906 may be dedicated to longer range wireless communications suchas GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

Processor 904 of computing device 900 includes an integrated circuit diepackaged within processor 904. In some implementations, the integratedcircuit die includes one or more of transistor layers 100, transistor300, transistor 600, and/or transistor 700 having stack 150, thusproviding low sheet resistance, as noted herein, such as with referenceto FIGS. 1-8. The term “processor” may refer to any device or portion ofa device that processes electronic data from registers and/or memory totransform that electronic data into other electronic data that may bestored in registers and/or memory. In some cases, processor 904 may be aSoC.

Communication chip 906 also includes an integrated circuit die packagedwithin communication chip 906. In accordance with anotherimplementation, a package including a communication chip incorporatesone or more of transistor layers 100, transistor 300, transistor 600,and/or transistor 700 having stack 150, thus providing low sheetresistance, as noted herein. In further implementations, anothercomponent housed within computing device 900 may contain amicroelectronic package including a fin device having cladding devicelayers such as described above.

In various implementations, computing device 900 may be a laptop, anetbook, a notebook, an ultrabook, a smartphone, a tablet, a personaldigital assistant (PDA), an ultra mobile PC, a mobile phone, a desktopcomputer, a server, a printer, a scanner, a monitor, a set-top box, anentertainment control unit, a digital camera, a portable music player,or a digital video recorder. In further implementations, computingdevice 900 may be any other electronic device that processes data.

Examples

The following examples pertain to embodiments.

Example 1 is a method to form transistor layers comprising: forming aGaN channel layer on a top surface of a substrate; forming a bi-layercapping stack on a top surface of the GaN layer, wherein forming thebi-layer capping stack includes: forming a lower capping layer of AlGaNmaterial on a top surface of an AlN layer formed on the top surface ofthe GaN layer; and forming an upper capping layer of AlInN material on atop surface of the AlGaN material.

In Example 2, the subject matter of Example 1 can optionally include,wherein the GaN layer comprises a GaN stack having a plurality of GaNlayers separated by AlN layers, and wherein the bi-layer capping stackcauses a sheet resistance of between 200 and 300 ohms per SQR in a 2 DEGchannel formed in a upper thickness of the GaN layer.

In Example 3, the subject matter of Example 1 can optionally include,wherein the AlGaN layer has a thickness of between 2 and 10 nm, and anelectron density of greater than 2.5 E13 cm/2; and wherein the AlInNlayer has a thickness of between 5 and 15 nm, and a channel mobility ofbetween 900 and 1000 CM2.

In Example 4, the subject matter of Example 1 can optionally include,wherein the AlGaN layer comprises Al_(X)Ga_((1-X))N, where X is lessthan 0.4; and wherein the AlInN layer is Al_(Y)In_((1-Y))N, where Y isgreater than 0.8.

In Example 5, the subject matter of Example 1 can optionally include,wherein a top surface of the AlGaN material forms a setback materialsurface upon which the AlInN material may be selectively etched.

In Example 6, the subject matter of Example 1 can optionally further becomprising: forming a gate over a top surface of the AlGaN layer; andforming junction regions on the AlInN layer on either side of the gate.

In Example 7, the subject matter of Example 6 can optionally include,wherein forming the gate comprises: selectively etching the AlInNmaterial to expose a top surface of the AlGaN material, whereinselectively etching the AlInN material comprises using a wet etchincluding a KOH or a NH4OH solution to selectively etch the AlInNmaterial but not etch the AlGaN material; forming a gate dielectric overthe exposed surface of the AlGaN material; and forming a metal gateelectrode on the gate dielectric.

In Example 8, the subject matter of Example 1 can optionally include,wherein the AlGaN layer has a predetermined thickness configured tocause electrons in a 2 DEG channel of the GaN material to be subject toless interface roughness scattering and less alloy scattering, and thusprovide a higher mobility than without the AlGaN layer.

In Example 9, the subject matter of Example 1 can optionally include,wherein forming the GaN layer comprises forming the GaN material in achamber at a temperature of approximately 1050 degrees Celsius (C);wherein forming the AlGaN layer comprises forming AlGaN in a chamber ata temperature of between 1000 and 1050 degrees C.; and wherein formingthe AlInN layer comprises forming AlInN material in a chamber at atemperature between 700 and 750 degrees C.

In Example 10, the subject matter of Example 1 can optionally include,wherein the transistor is part of one of a voltage regulator, a powermanagement integrated circuit (IC), a radio frequency (RF) poweramplifier, or a system on a chip (SoC).

Example 11 is transistor layers comprising: a GaN channel layer on a topsurface of a substrate; a bi-layer capping stack on a top surface of theGaN layer, wherein the bi-layer capping stack includes: a lower cappinglayer of AlGaN material on a top surface of an AlN layer on the topsurface of the GaN layer; and an upper capping layer of AlInN materialon a top surface of the AlGaN material.

In Example 12, the subject matter of Example 11 can optionally include,wherein the GaN layer comprises a GaN stack having a plurality of GaNlayers separated by AlN layers, and wherein the bi-layer capping stackcauses a sheet resistance of between 200 and 300 ohms per SQR in a 2 DEGchannel formed in a upper thickness of the GaN layer.

In Example 13, the subject matter of Example 11 can optionally include,wherein the AlGaN layer has a thickness of between 2 and 10 nm, and anelectron density of greater than 2.5 E13 cm/2; and wherein the AlInNlayer has a thickness of between 5 and 30 nm, and a channel mobility ofbetween 900 and 1400 CM2/V-s.

In Example 14, the subject matter of Example 11 can optionally include,wherein the AlGaN layer comprises Al_(X)Ga_((1-X))N, where X is lessthan 0.4; and wherein the AlInN layer is AlIn_((1-Y))N, where Y isgreater than 0.8.

In Example 15, the subject matter of Example 11 can optionally include,wherein a top surface of the AlGaN material forms a setback materialsurface upon which the AlInN material may be selectively etched.

In Example 16, the subject matter of Example 11 can optionally furtherbe comprising: a gate over a top surface of the AlGaN layer; andjunction regions on the AlInN layer on either side of the gate.

In Example 17, the subject matter of Example 16 can optionally include,wherein the gate comprises: a gate dielectric over an exposed surface ofthe AlGaN material in a trench; and a metal gate electrode on the gatedielectric in the trench.

In Example 18, the subject matter of Example 11 can optionally include,wherein the AlGaN layer has a predetermined thickness configured tocause electrons in a 2 DEG channel of the GaN material to be subject toless interface roughness scattering and less alloy scattering, and thusprovide a higher mobility than without the AlGaN layer.

In Example 19, the subject matter of Example 11 can optionally include,wherein the transistor is part of one of a voltage regulator, a powermanagement integrated circuit (IC), a radio frequency (RF) poweramplifier, or a system on a chip (SoC).

Example 20 is a system for computing comprising: a microprocessorcoupled to a memory, the microprocessor having at least one electronictransistor having transistor layers comprising: a GaN channel layer on atop surface of a substrate; a bi-layer capping stack on a top surface ofthe GaN layer, wherein the bi-layer capping stack includes: a lowercapping layer of AlGaN material on a top surface of an AlN layer on thetop surface of the GaN layer; and an upper capping layer of AlInNmaterial on a top surface of the AlGaN material.

In Example 21, the subject matter of Example 20 can optionally include,wherein the AlGaN layer has a thickness of between 2 and 10 nm, and anelectron density of greater than 2.5 E13 cm/2; and wherein the AlInNlayer has a thickness of between 5 and 15 nm, and a channel mobility ofbetween 900 and 1400 CM2/V-s, and wherein the bi-layer capping stackcauses a sheet resistance of between 200 and 300 ohms per SQR in a 2 DEGchannel formed in a upper thickness of the GaN layer.

In Example 22, the subject matter of Example 20 can optionally include,wherein the AlGaN layer comprises Al_(X)Ga_((1-X))N, where X is lessthan 0.4; and wherein the AlInN layer is Al_(Y)In_((1-Y))N, where Y isgreater than 0.8.

In Example 23, the subject matter of Example 20 can optionally befurther comprising: a gate over a top surface of the AlGaN layer,wherein the gate comprises: a gate dielectric over an exposed surface ofthe AlGaN material in a trench; and a metal gate electrode on the gatedielectric in the trench; and junction regions on the AlInN layer oneither side of the gate.

In Example 24, the subject matter of Example 20 can optionally include,wherein the transistor is part of one of a voltage regulator, a powermanagement integrated circuit (IC), a radio frequency (RF) poweramplifier, or a system on a chip (SoC).

Example 25 is an apparatus comprising means for performing the method ofany one of claims 1-10.

In the description above, for the purposes of explanation, numerousspecific details have been set forth in order to provide a thoroughunderstanding of the embodiments. It will be apparent however, to oneskilled in the art, that one or more other embodiments may be practicedwithout some of these specific details. The particular embodimentsdescribed are not provided to limit embodiments of the invention but toillustrate it. The scope of the embodiments of the invention is not tobe determined by the specific examples provided above but only by theclaims below. In other instances, well-known structures, devices, andoperations have been shown in block diagram form or without detail inorder to avoid obscuring the understanding of the description. Whereconsidered appropriate, reference numerals or terminal portions ofreference numerals have been repeated among the figures to indicatecorresponding or analogous elements, which may optionally have similarcharacteristics.

It should also be appreciated that reference throughout thisspecification to “one embodiment”, “an embodiment”, “one or moreembodiments”, or “different embodiments”, for example, means that aparticular feature may be included in the practice of the embodiments.Similarly, it should be appreciated that in the description variousfeatures are sometimes grouped together in a single embodiment, figure,or description thereof for the purpose of streamlining the disclosureand aiding in the understanding of various inventive aspects ofembodiments. This method of disclosure, however, is not to beinterpreted as reflecting an embodiment that requires more features thanare expressly recited in each claim. Rather, as the following claimsreflect, inventive aspects of embodiments that may lie in less than allfeatures of a single disclosed embodiment. For example, although thedescriptions and figures above describe forming planar or fin transistorlayers or transistors, the descriptions and figures above can be appliedto forming other transistor configurations including, for example,dual-gate, all around gate (AAG) (also referred to as gate all around),wire (e.g., nanowire), and other suitable transistor configurations.Thus, the claims following the Detailed Description are hereby expresslyincorporated into this Detailed Description, with each claim standing onits own as a separate embodiment of the invention.

What is claimed is:
 1. An integrated circuit structure, comprising: afin above a substrate, the fin comprising silicon, and the fin having atop and sidewalls; a first semiconductor layer on the top and sidewallsof the fin, the first semiconductor layer comprising gallium andnitrogen; a second semiconductor layer on the first semiconductor layeron the top and sidewalls of the fin, the second semiconductor layercomprising aluminum, gallium and nitrogen; a third semiconductor layeron the second semiconductor layer on the first semiconductor layer onthe top and sidewalls of the fin, the third semiconductor layercomprising aluminum, indium and nitrogen; a recess in the thirdsemiconductor layer, the recess exposing a portion of the secondsemiconductor layer on the first semiconductor layer on the top andsidewalls of the fin; and a gate electrode in the recess, the gateelectrode having a first side and a second side, wherein the thirdsemiconductor layer is on the first side and the second side of the gateelectrode.
 2. The integrated circuit structure of claim 1, furthercomprising: a first source/drain structure at a first end of the fin;and a second source/drain structure at a second end of the fin.
 3. Theintegrated circuit structure of claim 1, wherein the first semiconductorlayer has a thickness in the range of 10-100 nanometers.
 4. Theintegrated circuit structure of claim 1, wherein the secondsemiconductor layer has a thickness in the range of 2-10 nanometers. 5.The integrated circuit structure of claim 1, wherein the thirdsemiconductor layer has a thickness in the range of 5-10 nanometers. 6.The integrated circuit structure of claim 1, wherein the firstsemiconductor layer has a thickness in the range of 10-100 nanometers,wherein the second semiconductor layer has a thickness in the range of2-10 nanometers, and wherein the third semiconductor layer has athickness in the range of 5-10 nanometers.
 7. The integrated circuitstructure of claim 1, wherein the substrate is a semiconductorsubstrate, and the fin is on the semiconductor substrate.
 8. Theintegrated circuit structure of claim 1, wherein the semiconductorsubstrate is a single crystalline silicon substrate, and wherein the finis continuous with the single crystalline silicon substrate.
 9. Theintegrated circuit structure of claim 1, further comprising: a gatedielectric layer in the recess, wherein the gate electrode is on thegate dielectric layer.
 10. The integrated circuit structure of claim 9,wherein the gate dielectric layer comprises a high-k dielectricmaterial, and the gate electrode comprises a metal.
 11. A method offabricating an integrated circuit structure, the method comprising:forming a fin above a substrate, the fin comprising silicon, and the finhaving a top and sidewalls; forming a first semiconductor layer on thetop and sidewalls of the fin, the first semiconductor layer comprisinggallium and nitrogen; forming a second semiconductor layer on the firstsemiconductor layer on the top and sidewalls of the fin, the secondsemiconductor layer comprising aluminum, gallium and nitrogen; forming athird semiconductor layer on the second semiconductor layer on the firstsemiconductor layer on the top and sidewalls of the fin, the thirdsemiconductor layer comprising aluminum, indium and nitrogen; forming arecess in the third semiconductor layer, the recess exposing a portionof the second semiconductor layer on the first semiconductor layer onthe top and sidewalls of the fin; and forming a gate electrode in therecess, the gate electrode having a first side and a second side,wherein the third semiconductor layer is on the first side and thesecond side of the gate electrode.
 12. The method of claim 11, furthercomprising: forming a first source/drain structure at a first end of thefin; and forming a second source/drain structure at a second end of thefin.
 13. The method of claim 11, wherein the first semiconductor layerhas a thickness in the range of 10-100 nanometers.
 14. The method ofclaim 11, wherein the second semiconductor layer has a thickness in therange of 2-10 nanometers.
 15. The method of claim 11, wherein the thirdsemiconductor layer has a thickness in the range of 5-10 nanometers. 16.The method of claim 11, wherein the first semiconductor layer has athickness in the range of 10-100 nanometers, wherein the secondsemiconductor layer has a thickness in the range of 2-10 nanometers, andwherein the third semiconductor layer has a thickness in the range of5-10 nanometers.
 17. The method of claim 11, wherein the substrate is asemiconductor substrate, and the fin is on the semiconductor substrate.18. The method of claim 11, wherein the semiconductor substrate is asingle crystalline silicon substrate, and wherein the fin is continuouswith the single crystalline silicon substrate.
 19. The method of claim11, further comprising: forming a gate dielectric layer in the recess,wherein the gate electrode is on the gate dielectric layer.
 20. Themethod of claim 19, wherein the gate dielectric layer comprises a high-kdielectric material, and the gate electrode comprises a metal.